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[[I2Cデバイスを手で動かしてみる]]
* 背景, 概要 [#ic447942]
- I2Cのデバイスを、スイッチを手で ON/OFF して、間違えずに...
- I2Cのデバイスを、高速（一秒間に１０回以上）に「手」で操...
- tiny CPU でプログラムを実行することができるけど、tiny C...
- 配列に格納されたデータに従って、I2Cバスを操作したり、I2...
- tiny CPU をちょっと拡張して、配列を使えるようにしてみる...
- min CPU の命令セット、verilog など。ただし、verilog の...
-- http://www.cs.hiroshima-u.ac.jp/~nakano/wiki/wiki.cgi?...
----
* verilog の例 [#j4c13178]
-- ram.v には、配列 C に 0,1,2,3 を入れて、そのあと 配列 ...
-- tinyCPUと同じように動かします。
-- 各モジュールの先頭に, 適宜,
`timescale 1ns / 1ps
を入れてください。
- top.v
module top(sSegAnode, sSegCathode, sw, led, bu, bd, bl, ...
);
output [7:0] sSegAnode;
output [7:0] sSegCathode;
output [15:0] led;
input [15:0] sw;
input bu, bd, bl, br, bc, bclck;
wire BNx, BWx, BEx, BCx;
wire reset;
assign reset=~bd;
reg clk, run;
reg [15:0] in;
wire [2:0] cs;
wire [15:0] irout, qtop, dbus, out;
wire [11:0] pcout, abus;
chattering #(4) chattering0(.clk(bclck), .reset(reset)...
// assign BNx=BN;
// assign BWx=BW;
// assign BEx=BE;
// assign BCx=BC;
sSegArray sSegArray0(.clk(bclck), .reset(reset), .load...
.d({{1{0}},cs,abus,dbus}),
.anode(sSegAnode), .cathode(sSegCathode));
always @(posedge BCx, negedge reset) begin
if(!reset) clk<=0;
else
clk<=~clk;
end
minicpu minicpu0(.clk(clk), .reset(reset), .run(BNx), ...
.pcout(pcout), .irout(irout), .qtop(qtop), .ab...
endmodule
- defs.v
`define IDLE 3'b000
`define FETCHA 3'b001
`define FETCHB 3'b010
`define EXECA 3'b011
`define EXECB 3'b100
`define ADD 5'b00000
`define SUB 5'b00001
`define MUL 5'b00010
`define SHL 5'b00011
`define SHR 5'b00100
`define BAND 5'b00101
`define BOR 5'b00110
`define BXOR 5'b00111
`define AND 5'b01000
`define OR 5'b01001
`define EQ 5'b01010
`define NE 5'b01011
`define GE 5'b01100
`define LE 5'b01101
`define GT 5'b01110
`define LT 5'b01111
`define NEG 5'b10000
`define BNOT 5'b10001
`define NOT 5'b10010
`define HALT 4'b0000
`define PUSHI 4'b0001
`define PUSH 4'b0010
`define POP 4'b0011
`define JMP 4'b0100
`define JZ 4'b0101
`define JNZ 4'b0110
`define LD 4'b0111
`define ST 4'b1000
`define IN 4'b1101
`define OUT 4'b1110
`define OP 4'b1111
- minicpu.v (高速化してません。)
`include "defs.v"
module minicpu(clk, reset, run, in, cs, pcout, irout, qt...
);
input clk,reset, run;
input [15:0] in;
output [2:0] cs;
output [15:0] irout, qtop, dbus, out;
output [11:0] pcout, abus;
wire [15:0] qnext, ramout, aluout;
reg [11:0] abus;
reg halt, cont, pcinc, push, pop, abus2pc, dbus2ir, dbus...
dbus2obuf, pc2abus, ir2abus, ir2dbus, qtop2dbus, qnext2d...
counter #(12) pc0(.clk(clk), .reset(reset), .load(abus2p...
.inc(pcinc), .d(abus), .q(pcout));
counter #(16) ir0(.clk(clk), .reset(reset), .load(dbus2i...
.inc(0), .d(dbus), .q(irout));
state state0(.clk(clk), .reset(reset), .run(run),
.halt(halt), .cont(cont), .cs(cs));
stack stack0(.clk(clk), .reset(reset), .load(dbus2qtop),...
.d(dbus), .qtop(qtop), .qnext(qnext));
alu alu0(.a(qtop), .b(qnext), .f(irout[4:0]), .s(aluout));
ram #(16,12,4096) ram0(.clk(clk), .load(dbus2ram),
.addr(abus), .d(dbus), .q(ramout));
counter #(16) obuf0(.clk(clk), .reset(reset), .load(dbus...
.inc(0), .d(dbus), .q(out));
always @(pc2abus or ir2abus or pcout or irout or qtop2ab...
if(pc2abus) abus = pcout;
else if(ir2abus) abus = irout[11:0];
else if(qtop2abus) abus = qtop[11:0];
else if(qnext2abus) abus = qnext[11:0];
else abus = 12'hxxx;
assign dbus = ir2dbus ? {{4{irout[11]}},irout[11:0]} : 1...
assign dbus = qtop2dbus ? qtop : 16'hzzzz;
assign dbus = alu2dbus ? aluout : 16'hzzzz;
assign dbus = ram2dbus ? ramout : 16'hzzzz;
assign dbus = in2dbus ? in : 16'hzzzz;
assign dbus = qnext2dbus? qnext[11:0] : 16'hzzz;
always @(cs or irout or qtop)
begin
halt = 0; cont = 0; pcinc = 0; push = 0; pop = 0; abus...
dbus2qtop = 0; dbus2ram = 0; dbus2obuf = 0; pc2abus = ...
ir2dbus = 0; qtop2dbus = 0; alu2dbus = 0; ram2dbus = 0...
if(cs == `FETCHA)
begin
pcinc = 1; pc2abus = 1;
end
else if(cs == `FETCHB)
begin
ram2dbus = 1; dbus2ir = 1;
end
else if(cs == `EXECA)
case(irout[15:12])
`PUSHI:
begin
ir2dbus = 1; dbus2qtop = 1; push = 1;
end
`PUSH:
begin
ir2abus = 1; cont = 1;
end
`LD:
begin
qtop2abus = 1; cont = 1; pop=1;
end
`POP:
begin
ir2abus = 1; qtop2dbus =1; dbus2ram = 1; pop = 1;
end
`ST:
begin
qtop2dbus = 1; dbus2ram=1; qnext2abus=1; pop = 1;...
end
`JMP:
begin
ir2abus = 1; abus2pc = 1;
end
`JZ:
begin
if(qtop==0)
begin
ir2abus = 1; abus2pc = 1;
end
pop = 1;
end
`JNZ:
begin
if(qtop !=0)
begin
ir2abus = 1; abus2pc = 1;
end
pop = 1;
end
`IN:
begin
in2dbus = 1; dbus2qtop = 1; push = 1;
end
`OUT:
begin
qtop2dbus = 1; dbus2obuf = 1; pop = 1;
end
`OP:
begin
alu2dbus = 1; dbus2qtop = 1;
if(irout[4] ==0) pop = 1;
end
default:
halt = 1;
endcase
else if(cs == `EXECB)
begin
if(irout[15:12] == `PUSH|| irout[15:12] == `LD)
begin
ram2dbus = 1; dbus2qtop = 1; push = 1;
end
else
if(irout[15:12] == `ST)
begin
pop = 1;
end
end
end
endmodule
- state.v
`include "defs.v"
module state(clk, reset, run, cont, halt, cs
);
input clk, reset, run, cont, halt;
output [2:0] cs;
reg [2:0] cs;
always @(posedge clk or negedge reset)
if(!reset) cs<= `IDLE;
else
case(cs)
`IDLE: if(run) cs <= `FETCHA;
`FETCHA: cs <= `FETCHB;
`FETCHB: cs <= `EXECA;
`EXECA: if(halt) cs <= `IDLE;
else if(cont) cs <= `EXECB;
else cs <= `FETCHA;
`EXECB: cs <= `FETCHA;
default: cs <= 3'bxxx;
endcase
endmodule
- stack.v
module stack(clk, reset, load, push, pop, d, qtop, qnext...
parameter N=8;
input clk, reset, load, push, pop;
input [15:0] d;
output [15:0] qtop, qnext;
reg [15:0] q [N-1:0];
assign qtop = q[0];
assign qnext = q[1];
always @(posedge clk or negedge reset)
if(!reset) q[0] <= 0;
else if(load) q[0] <= d;
else if(pop) q[0] <= q[1];
//integer i;
generate
genvar i;
for(i=1;i<N-1; i=i+1)
begin : for_i
always @(posedge clk or negedge reset)
if(!reset) q[i] <=0;
else if(push) q[i] <=q[i-1];
else if(pop) q[i] <=q[i+1];
end
endgenerate
always @(posedge clk or negedge reset)
if(!reset) q[N-1] <= 0;
else if(push) q[N-1] <= q[N-2];
endmodule
- alu.v
`include "defs.v"
module alu(a,b,f,s);
input [15:0] a,b;
input [4:0] f;
output [15:0] s;
reg [15:0] s;
wire [15:0] x,y;
assign x=a+16'h8000;
assign y=b+16'h8000;
always @(a or b or x or y or f)
case(f)
`ADD : s = b + a;
`SUB : s = b - a;
`MUL : s = b * a;
`SHL : s = b << a;
`SHR : s = b >> a;
`BAND : s = b & a;
`BOR : s = b | a;
`BXOR : s = b ^ a;
`AND : s = b && a;
`OR : s = b || a;
`EQ : s = b == a;
`NE : s = b != a;
`GE : s = x >= y;
`LE : s = x <= y;
`GT : s = x > y;
`LT : s = x < y;
`NEG : s= -a;
`BNOT : s= ~a;
`NOT : s = !a;
default : s = 16'hxxxx;
endcase
endmodule
- ram.v
module ram(clk, load, addr, d, q
);
parameter DWIDTH=16, AWIDTH=12, WORDS=4096;
input clk, load;
input [AWIDTH-1:0] addr;
input [DWIDTH-1:0] d;
output [DWIDTH-1:0] q;
reg [DWIDTH-1:0] q;
reg [DWIDTH-1:0] mem [WORDS-1:0];
always @(posedge clk)
begin
if(load) mem[addr] <= d;
q <= mem[addr];
end
integer i;
initial begin
for(i=0; i<WORDS; i=i+1)
mem[i]=12'h000;
mem[8'h00] = 16'h1000; // PUSHI 0
mem[8'h01] = 16'h3021; // POP i ... i=0;
mem[8'h02] = 16'h2021; // L1 PUSH i
mem[8'h03] = 16'h1023; // PUSHI C
mem[8'h04] = 16'hF000; // ADD
mem[8'h05] = 16'h2021; // PUSH i
mem[8'h06] = 16'h8000; // ST ... C[i]=i;
mem[8'h07] = 16'h2021; // PUSH i
mem[8'h08] = 16'h1001; // PUSHI 1
mem[8'h09] = 16'hF000; // ADD
mem[8'h0A] = 16'h3021; // POP i .... i++;
mem[8'h0B] = 16'h2021; // PUSH i
mem[8'h0C] = 16'h201F; // PUSH n
mem[8'h0D] = 16'hF001; // SUB
mem[8'h0E] = 16'h6002; // JNZ L1: if(i<n) goto L1;
mem[8'h0F] = 16'h1000; // PUSHI 0
mem[8'h10] = 16'h3022; // POP j .... j=0;
mem[8'h11] = 16'h2022; // L2: PUSH j
mem[8'h12] = 16'h1023; // PUSHI C
mem[8'h13] = 16'hF000; // ADD
mem[8'h14] = 16'h7000; // LD
mem[8'h15] = 16'hE000; // OUT print(C[j]);
mem[8'h16] = 16'h2022; // PUSH j
mem[8'h17] = 16'h1001; // PUSHI 1
mem[8'h18] = 16'hF000; // ADD
mem[8'h19] = 16'h3022; // POP j j++
mem[8'h1A] = 16'h2022; // PUSH j
mem[8'h1B] = 16'h2020; // PUSH m
mem[8'h1C] = 16'hF001; // SUB
mem[8'h1D] = 16'h6011; // JNZ L2: if(j<m) goto L2
mem[8'h1E] = 16'h0000; // L3: HALT
mem[8'h1F] = 16'h0004; // n: 4
mem[8'h20] = 16'h0010; // m: 16
mem[8'h21] = 16'h0000; // i:
mem[8'h22] = 16'h0000; // j: 0
mem[8'h23] = 16'h0000; // C:
mem[8'h24] = 16'h0000; //
mem[8'h25] = 16'h0000; //
mem[8'h26] = 16'h0000; //
mem[8'h27] = 16'h0001; // D: 1
mem[8'h28] = 16'h0000; // 0
mem[8'h29] = 16'h0002; // 2
mem[8'h2A] = 16'h0000; // 0
mem[8'h2B] = 16'h0004; // 4
mem[8'h2C] = 16'h0000; // 0
mem[8'h2D] = 16'h0005; // 5
mem[8'h2E] = 16'h0000; // 0
mem[8'h2F] = 16'h000A; // A
mem[8'h30] = 16'h0000; // 0
mem[8'h31] = 16'h0008; // 8
mem[8'h32] = 16'h0000; // 0
end
endmodule
- counter.v
module counter(clk, reset, load, inc, d, q );
parameter N=16;
input clk, reset, load, inc;
input [N-1:0] d;
output [N-1:0] q;
reg [N-1:0] q;
always @(posedge clk or negedge reset)
if(!reset) q <=0;
else if(load) q<=d;
else if(inc) q<=q+1;
endmodule
- chattering.v
module chattering(clk, reset, in, out
);
parameter N=1;
input clk, reset;
input [N-1:0]in;
output [N-1:0]out;
reg [N-1:0]out;
reg [21:0] count;
always @(posedge clk or negedge reset)
if(!reset) count <=0;
else count <= count +1;
always @(posedge clk)
if(count==0) out <= in;
endmodule
- sSegArray.v
module sSegArray(
clk,reset,load,d,
anode, cathode
);
parameter N=32;
input clk,reset,load;
input [N-1:0] d;
output [7:0] anode;
output [7:0] cathode;
reg [7:0] anode;
reg [7:0] cathode;
reg [31:0] q;
wire [2:0] selectedSeg;
wire [7:0] wOneSeg;
reg segClk;
counter #(8) waitOneSeg(.clk(clk), .reset(reset), .load(...
//assign segClk= (wOneSeg==0)? ~segClk: segClk;
always @(posedge clk, negedge reset) begin
if(!reset) segClk<=0;
else
if (wOneSeg==0) segClk<=~segClk;
end
counter #(3) selector(.clk(segClk),.reset(reset),.load(0...
//counter #(3) selector(.clk(clk), .reset(reset), .load(...
always @(posedge clk, negedge reset)
begin
if(!reset) anode=8'hFE; // note! anode is connected...
else // in order to active one 7s...
case (selectedSeg)
3'b000: anode=8'hFE;
3'b001: anode=8'hFD;
3'b010: anode=8'hFB;
3'b011: anode=8'hF7;
3'b100: anode=8'hEF;
3'b101: anode=8'hDF;
3'b110: anode=8'hBF;
3'b111: anode=8'h7F;
endcase
end
reg [3:0] selectedVal;
always @(posedge clk, negedge reset)
begin
if(!reset) cathode=8'h03; // note! ...
else // and i...
case (selectedVal) // ...
4'b0000: cathode=8'h03; //8'hfc; 0 -...
4'b0001: cathode=8'h9f; //8'h60; 1 /...
4'b0010: cathode=8'h25; //8'hda; 2 /...
4'b0011: cathode=8'h0d; //8'hf2; 3 / ...
4'b0100: cathode=8'h99; //8'h66; 4 --...
4'b0101: cathode=8'h49; //8'hb6; 5 / cg...
4'b0110: cathode=8'h41; //8'hbe; 6 /ce...
4'b0111: cathode=8'h1f; //8'he0; 7 / ...
4'b1000: cathode=8'h01; //8'hfe; 8 --...
4'b1001: cathode=8'h09; //8'hf6; 9 ...
4'b1010: cathode=8'h11; //8'hee; A
4'b1011: cathode=8'hc1; //8'h3e; B
4'b1100: cathode=8'h63; //8'h9c; C
4'b1101: cathode=8'h85; //8'h7c; D
4'b1110: cathode=8'h61; //8'h9e; E
4'b1111: cathode=8'h71; //8'h8e; F
endcase
end
always @(posedge clk, negedge reset)
begin
if(!reset) selectedVal=q[3:0];
else
case (selectedSeg)
3'b000: selectedVal=q[3:0];
3'b001: selectedVal=q[7:4];
3'b010: selectedVal=q[11:8];
3'b011: selectedVal=q[15:12];
3'b100: selectedVal=q[19:16];
3'b101: selectedVal=q[23:20];
3'b110: selectedVal=q[27:24];
3'b111: selectedVal=q[31:28];
endcase
end
always @(posedge clk, negedge reset)
begin
if(!reset) q=0;
else
if(load) q=d;
end
endmodule
- top.xdc (vivadoの場合)
## Clock signal
##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name...
set_property PACKAGE_PIN E3 [get_ports bclck]
set_property IOSTANDARD LVCMOS33 [get_ports bclck]
# create_clock -add -name sys_clk_pin -period 10.00 -wa...
## Switches
##Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name ...
set_property PACKAGE_PIN U9 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
##Bank = 34, Pin name = IO_25_34, Sch name = SW1
set_property PACKAGE_PIN U8 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
##Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2
set_property PACKAGE_PIN R7 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
##Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3
set_property PACKAGE_PIN R6 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
##Bank = 34, Pin name = IO_L19N_T3_VREF_34, Sch name...
set_property PACKAGE_PIN R5 [get_ports {sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
##Bank = 34, Pin name = IO_L20P_T3_34, Sch name = SW5
set_property PACKAGE_PIN V7 [get_ports {sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
##Bank = 34, Pin name = IO_L20N_T3_34, Sch name = SW6
set_property PACKAGE_PIN V6 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
##Bank = 34, Pin name = IO_L10P_T1_34, Sch name = SW7
set_property PACKAGE_PIN V5 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
##Bank = 34, Pin name = IO_L8P_T1-34, Sch name = SW8
set_property PACKAGE_PIN U4 [get_ports {sw[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
##Bank = 34, Pin name = IO_L9N_T1_DQS_34, Sch name =...
set_property PACKAGE_PIN V2 [get_ports {sw[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
##Bank = 34, Pin name = IO_L9P_T1_DQS_34, Sch name =...
set_property PACKAGE_PIN U2 [get_ports {sw[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
##Bank = 34, Pin name = IO_L11N_T1_MRCC_34, Sch name...
set_property PACKAGE_PIN T3 [get_ports {sw[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
##Bank = 34, Pin name = IO_L17N_T2_34, Sch name = S...
set_property PACKAGE_PIN T1 [get_ports {sw[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
##Bank = 34, Pin name = IO_L11P_T1_SRCC_34, Sch name...
set_property PACKAGE_PIN R3 [get_ports {sw[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
##Bank = 34, Pin name = IO_L14N_T2_SRCC_34, Sch name...
set_property PACKAGE_PIN P3 [get_ports {sw[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
##Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name...
set_property PACKAGE_PIN P4 [get_ports {sw[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
## LEDs
##Bank = 34, Pin name = IO_L24N_T3_34, Sch name = L...
set_property PACKAGE_PIN T8 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
##Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name ...
set_property PACKAGE_PIN V9 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
##Bank = 34, Pin name = IO_L24P_T3_34, Sch name = L...
set_property PACKAGE_PIN R8 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
##Bank = 34, Pin name = IO_L23N_T3_34, Sch name = L...
set_property PACKAGE_PIN T6 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
##Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name...
set_property PACKAGE_PIN T5 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
##Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name...
set_property PACKAGE_PIN T4 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
##Bank = 34, Pin name = IO_L22P_T3_34, Sch name = L...
set_property PACKAGE_PIN U7 [get_ports {led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
##Bank = 34, Pin name = IO_L22N_T3_34, Sch name = L...
set_property PACKAGE_PIN U6 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
##Bank = 34, Pin name = IO_L10N_T1_34, Sch name = L...
set_property PACKAGE_PIN V4 [get_ports {led[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
##Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9
set_property PACKAGE_PIN U3 [get_ports {led[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
##Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LE...
set_property PACKAGE_PIN V1 [get_ports {led[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
##Bank = 34, Pin name = IO_L17P_T2_34, Sch name = L...
set_property PACKAGE_PIN R1 [get_ports {led[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
##Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name...
set_property PACKAGE_PIN P5 [get_ports {led[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
##Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LE...
set_property PACKAGE_PIN U1 [get_ports {led[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
##Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name ...
set_property PACKAGE_PIN R2 [get_ports {led[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
##Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name ...
set_property PACKAGE_PIN P2 [get_ports {led[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LE...
#set_property PACKAGE_PIN K5 [get_ports {cled1[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {cled1[2]}]
##Bank = 15, Pin name = IO_L5P_T0_AD9P_15, Sch name ...
#set_property PACKAGE_PIN F13 [get_ports {cled1[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {cled1[1]}]
##Bank = 35, Pin name = IO_L19N_T3_VREF_35, Sch name...
#set_property PACKAGE_PIN F6 [get_ports {cled1[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {cled1[0]}]
##Bank = 34, Pin name = IO_0_34, Sch name = LED17_R
#set_property PACKAGE_PIN K6 [get_ports {cled2[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {cled2[2]}]
##Bank = 35, Pin name = IO_24P_T3_35, Sch name = L...
#set_property PACKAGE_PIN H6 [get_ports {cled2[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {cled2[1]}]
##Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14, S...
#set_property PACKAGE_PIN L16 [get_ports {cled2[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {cled2[0]}]
##7 segment display
##Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA
set_property PACKAGE_PIN L3 [get_ports {sSegCathode[7]}]...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathod...
##Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name =...
set_property PACKAGE_PIN N1 [get_ports {sSegCathode[6]}]...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathod...
##Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name ...
set_property PACKAGE_PIN L5 [get_ports {sSegCathode[5]}]...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathod...
##Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD
set_property PACKAGE_PIN L4 [get_ports {sSegCathode[4]}]...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathod...
##Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE
set_property PACKAGE_PIN K3 [get_ports {sSegCathode[3]}]...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathod...
##Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF
set_property PACKAGE_PIN M2 [get_ports {sSegCathode[2]}]...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathod...
##Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG
set_property PACKAGE_PIN L6 [get_ports {sSegCathode[1]}]...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathod...
##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP
set_property PACKAGE_PIN M4 [get_ports sSegCathode[0]] ...
set_property IOSTANDARD LVCMOS33 [get_ports sSegCathode...
##Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0
set_property PACKAGE_PIN N6 [get_ports {sSegAnode[0]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1
set_property PACKAGE_PIN M6 [get_ports {sSegAnode[1]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2
set_property PACKAGE_PIN M3 [get_ports {sSegAnode[2]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name ...
set_property PACKAGE_PIN N5 [get_ports {sSegAnode[3]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name =...
set_property PACKAGE_PIN N2 [get_ports {sSegAnode[4]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5
set_property PACKAGE_PIN N4 [get_ports {sSegAnode[5]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6
set_property PACKAGE_PIN L1 [get_ports {sSegAnode[6]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7
set_property PACKAGE_PIN M1 [get_ports {sSegAnode[7]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Buttons
##Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15, Sch na...
#set_property PACKAGE_PIN C12 [get_ports btnCpuReset]
#set_property IOSTANDARD LVCMOS33 [get_ports btnCpuReset]
##Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name...
set_property PACKAGE_PIN E16 [get_ports bc]
set_property IOSTANDARD LVCMOS33 [get_ports bc]
##Bank = 15, Pin name = IO_L14P_T2_SRCC_15, Sch name...
set_property PACKAGE_PIN F15 [get_ports bu]
set_property IOSTANDARD LVCMOS33 [get_ports bu]
##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14...
set_property PACKAGE_PIN T16 [get_ports bl]
set_property IOSTANDARD LVCMOS33 [get_ports bl]
##Bank = 14, Pin name = IO_25_14, Sch name = BTNR
set_property PACKAGE_PIN R10 [get_ports br]
set_property IOSTANDARD LVCMOS33 [get_ports br]
##Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name ...
set_property PACKAGE_PIN V10 [get_ports bd]
set_property IOSTANDARD LVCMOS33 [get_ports bd]
##Temperature Sensor
##Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name...
#set_property PACKAGE_PIN F16 [get_ports scl]
#set_property IOSTANDARD LVCMOS33 [get_ports scl]
##Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name...
#set_property PACKAGE_PIN G16 [get_ports sda]
#set_property IOSTANDARD LVCMOS33 [get_ports sda]
##Bank = 15, Pin name = IO_L1P_T0_AD0P_15, Sch name ...
#set_property PACKAGE_PIN D14 [get_ports tmpInt]
#set_property IOSTANDARD LVCMOS33 [get_ports tmpInt]
##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name ...
#set_property PACKAGE_PIN C14 [get_ports tmpCT]
#set_property IOSTANDARD LVCMOS33 [get_ports tmpCT]
- top.ucf (ISEの場合)
## This file is a general .ucf for the Nexys4 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used signals according to the project
## Clock signal
NET "bclck" LOC = "E3" | IOSTANDARD = "LVCMOS33"; ...
#NET "clk" TNM_NET = sys_clk_pin;
#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100 MHz HI...
## Switches
NET "sw<0>" LOC = "U9" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<1>" LOC = "U8" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<2>" LOC = "R7" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<3>" LOC = "R6" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<4>" LOC = "R5" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<5>" LOC = "V7" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<6>" LOC = "V6" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<7>" LOC = "V5" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<8>" LOC = "U4" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<9>" LOC = "V2" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<10>" LOC = "U2" | IOSTANDARD = "LVCMOS33"; #B...
NET "sw<11>" LOC = "T3" | IOSTANDARD = "LVCMOS33"; #B...
NET "sw<12>" LOC = "T1" | IOSTANDARD = "LVCMOS33"; #B...
NET "sw<13>" LOC = "R3" | IOSTANDARD = "LVCMOS33"; #B...
NET "sw<14>" LOC = "P3" | IOSTANDARD = "LVCMOS33"; #B...
NET "sw<15>" LOC = "P4" | IOSTANDARD = "LVCMOS33"; #B...
## LEDs
NET "led<0>" LOC = "T8" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<1>" LOC = "V9" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<2>" LOC = "R8" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<3>" LOC = "T6" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<4>" LOC = "T5" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<5>" LOC = "T4" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<6>" LOC = "U7" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<7>" LOC = "U6" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<8>" LOC = "V4" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<9>" LOC = "U3" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<10>" LOC = "V1" | IOSTANDARD = "LVCMOS33"; #...
NET "led<11>" LOC = "R1" | IOSTANDARD = "LVCMOS33"; #...
NET "led<12>" LOC = "P5" | IOSTANDARD = "LVCMOS33"; #...
NET "led<13>" LOC = "U1" | IOSTANDARD = "LVCMOS33"; #...
NET "led<14>" LOC = "R2" | IOSTANDARD = "LVCMOS33"; #...
NET "led<15>" LOC = "P2" | IOSTANDARD = "LVCMOS33"; #...
#NET "RGB1_Red" LOC = "K5" | IOSTANDARD = "LVCMOS33"; ...
#NET "RGB1_Green" LOC = "F13" | IOSTANDARD = "LVCMOS33"...
#NET "RGB1_Blue" LOC = "F6" | IOSTANDARD = "LVCMOS33"; ...
#NET "RGB2_Red" LOC = "K6" | IOSTANDARD = "LVCMOS33"; ...
#NET "RGB2_Green" LOC = "H6" | IOSTANDARD = "LVCMOS33";...
#NET "RGB2_Blue" LOC = "L16" | IOSTANDARD = "LVCMOS33";...
## 7 segment display
NET "sSegCathode<7>" LOC = "L3" | IOSTANDARD = "LVCMOS...
NET "sSegCathode<6>" LOC = "N1" | IOSTANDARD = "LVCMOS...
NET "sSegCathode<5>" LOC = "L5" | IOSTANDARD = "LVCMOS...
NET "sSegCathode<4>" LOC = "L4" | IOSTANDARD = "LVCMOS...
NET "sSegCathode<3>" LOC = "K3" | IOSTANDARD = "LVCMOS...
NET "sSegCathode<2>" LOC = "M2" | IOSTANDARD = "LVCMOS...
NET "sSegCathode<1>" LOC = "L6" | IOSTANDARD = "LVCMOS...
NET "sSegCathode<0>" LOC = "M4" | IOSTANDARD = "LVCMO...
NET "sSegAnode<0>" LOC = "N6" | IOSTANDARD = "LVCMOS33...
NET "sSegAnode<1>" LOC = "M6" | IOSTANDARD = "LVCMOS33...
NET "sSegAnode<2>" LOC = "M3" | IOSTANDARD = "LVCMOS33...
NET "sSegAnode<3>" LOC = "N5" | IOSTANDARD = "LVCMOS33...
NET "sSegAnode<4>" LOC = "N2" | IOSTANDARD = "LVCMOS33...
NET "sSegAnode<5>" LOC = "N4" | IOSTANDARD = "LVCMOS33...
NET "sSegAnode<6>" LOC = "L1" | IOSTANDARD = "LVCMOS33...
NET "sSegAnode<7>" LOC = "M1" | IOSTANDARD = "LVCMOS33...
## Buttons
#NET "btnCpuReset" LOC = "C12" | IOSTANDARD = "LVCMOS33...
NET "bc" LOC = "E16" | IOSTANDARD = "LVCMOS33"; #Ban...
NET "bu" LOC = "F15" | IOSTANDARD = "LVCMOS33"; #Ban...
NET "bl" LOC = "T16" | IOSTANDARD = "LVCMOS33"; #Ban...
NET "br" LOC = "R10" | IOSTANDARD = "LVCMOS33"; #Ban...
NET "bd" LOC = "V10" | IOSTANDARD = "LVCMOS33"; #Ban...
* 動かし方 [#k3a2a93b]
** Nexys4へのbitファイル書き込み [#id3441e9]
- 上のソースを使ってVivadoかISEで bit ファイルを生成し, N...
-- Nexys4のBTNC(bc)を minicpu の clock ボタン, BTNU(bu)を...
-- Nexys4の8桁の7セグメント LEDの、いちばん左の桁はminiCP...
-- 7セグメントLEDの左から２桁目、３桁目、４桁目は、 minic...
-- Nexyx4の16個のLEDは, minicpuの出力バッファの出力(out)...
** CPUの実行 [#xb98452f]
- bd(reset)をクリックしてcpuをresetします。
- bu(run) を押して、そのままbc(bclck)を押して離して最初の...
- bcを何度も押して離して、cpuにclockを供給し、実行を進め...
- 一番左の桁が1(fetch a state)のときの、左から２桁目から...
- 上のプログラムは配列Cに、0,1,2,3を代入し、その内容を出...
----
#counter
終了行:
[[I2Cデバイスを手で動かしてみる]]
* 背景, 概要 [#ic447942]
- I2Cのデバイスを、スイッチを手で ON/OFF して、間違えずに...
- I2Cのデバイスを、高速（一秒間に１０回以上）に「手」で操...
- tiny CPU でプログラムを実行することができるけど、tiny C...
- 配列に格納されたデータに従って、I2Cバスを操作したり、I2...
- tiny CPU をちょっと拡張して、配列を使えるようにしてみる...
- min CPU の命令セット、verilog など。ただし、verilog の...
-- http://www.cs.hiroshima-u.ac.jp/~nakano/wiki/wiki.cgi?...
----
* verilog の例 [#j4c13178]
-- ram.v には、配列 C に 0,1,2,3 を入れて、そのあと 配列 ...
-- tinyCPUと同じように動かします。
-- 各モジュールの先頭に, 適宜,
`timescale 1ns / 1ps
を入れてください。
- top.v
module top(sSegAnode, sSegCathode, sw, led, bu, bd, bl, ...
);
output [7:0] sSegAnode;
output [7:0] sSegCathode;
output [15:0] led;
input [15:0] sw;
input bu, bd, bl, br, bc, bclck;
wire BNx, BWx, BEx, BCx;
wire reset;
assign reset=~bd;
reg clk, run;
reg [15:0] in;
wire [2:0] cs;
wire [15:0] irout, qtop, dbus, out;
wire [11:0] pcout, abus;
chattering #(4) chattering0(.clk(bclck), .reset(reset)...
// assign BNx=BN;
// assign BWx=BW;
// assign BEx=BE;
// assign BCx=BC;
sSegArray sSegArray0(.clk(bclck), .reset(reset), .load...
.d({{1{0}},cs,abus,dbus}),
.anode(sSegAnode), .cathode(sSegCathode));
always @(posedge BCx, negedge reset) begin
if(!reset) clk<=0;
else
clk<=~clk;
end
minicpu minicpu0(.clk(clk), .reset(reset), .run(BNx), ...
.pcout(pcout), .irout(irout), .qtop(qtop), .ab...
endmodule
- defs.v
`define IDLE 3'b000
`define FETCHA 3'b001
`define FETCHB 3'b010
`define EXECA 3'b011
`define EXECB 3'b100
`define ADD 5'b00000
`define SUB 5'b00001
`define MUL 5'b00010
`define SHL 5'b00011
`define SHR 5'b00100
`define BAND 5'b00101
`define BOR 5'b00110
`define BXOR 5'b00111
`define AND 5'b01000
`define OR 5'b01001
`define EQ 5'b01010
`define NE 5'b01011
`define GE 5'b01100
`define LE 5'b01101
`define GT 5'b01110
`define LT 5'b01111
`define NEG 5'b10000
`define BNOT 5'b10001
`define NOT 5'b10010
`define HALT 4'b0000
`define PUSHI 4'b0001
`define PUSH 4'b0010
`define POP 4'b0011
`define JMP 4'b0100
`define JZ 4'b0101
`define JNZ 4'b0110
`define LD 4'b0111
`define ST 4'b1000
`define IN 4'b1101
`define OUT 4'b1110
`define OP 4'b1111
- minicpu.v (高速化してません。)
`include "defs.v"
module minicpu(clk, reset, run, in, cs, pcout, irout, qt...
);
input clk,reset, run;
input [15:0] in;
output [2:0] cs;
output [15:0] irout, qtop, dbus, out;
output [11:0] pcout, abus;
wire [15:0] qnext, ramout, aluout;
reg [11:0] abus;
reg halt, cont, pcinc, push, pop, abus2pc, dbus2ir, dbus...
dbus2obuf, pc2abus, ir2abus, ir2dbus, qtop2dbus, qnext2d...
counter #(12) pc0(.clk(clk), .reset(reset), .load(abus2p...
.inc(pcinc), .d(abus), .q(pcout));
counter #(16) ir0(.clk(clk), .reset(reset), .load(dbus2i...
.inc(0), .d(dbus), .q(irout));
state state0(.clk(clk), .reset(reset), .run(run),
.halt(halt), .cont(cont), .cs(cs));
stack stack0(.clk(clk), .reset(reset), .load(dbus2qtop),...
.d(dbus), .qtop(qtop), .qnext(qnext));
alu alu0(.a(qtop), .b(qnext), .f(irout[4:0]), .s(aluout));
ram #(16,12,4096) ram0(.clk(clk), .load(dbus2ram),
.addr(abus), .d(dbus), .q(ramout));
counter #(16) obuf0(.clk(clk), .reset(reset), .load(dbus...
.inc(0), .d(dbus), .q(out));
always @(pc2abus or ir2abus or pcout or irout or qtop2ab...
if(pc2abus) abus = pcout;
else if(ir2abus) abus = irout[11:0];
else if(qtop2abus) abus = qtop[11:0];
else if(qnext2abus) abus = qnext[11:0];
else abus = 12'hxxx;
assign dbus = ir2dbus ? {{4{irout[11]}},irout[11:0]} : 1...
assign dbus = qtop2dbus ? qtop : 16'hzzzz;
assign dbus = alu2dbus ? aluout : 16'hzzzz;
assign dbus = ram2dbus ? ramout : 16'hzzzz;
assign dbus = in2dbus ? in : 16'hzzzz;
assign dbus = qnext2dbus? qnext[11:0] : 16'hzzz;
always @(cs or irout or qtop)
begin
halt = 0; cont = 0; pcinc = 0; push = 0; pop = 0; abus...
dbus2qtop = 0; dbus2ram = 0; dbus2obuf = 0; pc2abus = ...
ir2dbus = 0; qtop2dbus = 0; alu2dbus = 0; ram2dbus = 0...
if(cs == `FETCHA)
begin
pcinc = 1; pc2abus = 1;
end
else if(cs == `FETCHB)
begin
ram2dbus = 1; dbus2ir = 1;
end
else if(cs == `EXECA)
case(irout[15:12])
`PUSHI:
begin
ir2dbus = 1; dbus2qtop = 1; push = 1;
end
`PUSH:
begin
ir2abus = 1; cont = 1;
end
`LD:
begin
qtop2abus = 1; cont = 1; pop=1;
end
`POP:
begin
ir2abus = 1; qtop2dbus =1; dbus2ram = 1; pop = 1;
end
`ST:
begin
qtop2dbus = 1; dbus2ram=1; qnext2abus=1; pop = 1;...
end
`JMP:
begin
ir2abus = 1; abus2pc = 1;
end
`JZ:
begin
if(qtop==0)
begin
ir2abus = 1; abus2pc = 1;
end
pop = 1;
end
`JNZ:
begin
if(qtop !=0)
begin
ir2abus = 1; abus2pc = 1;
end
pop = 1;
end
`IN:
begin
in2dbus = 1; dbus2qtop = 1; push = 1;
end
`OUT:
begin
qtop2dbus = 1; dbus2obuf = 1; pop = 1;
end
`OP:
begin
alu2dbus = 1; dbus2qtop = 1;
if(irout[4] ==0) pop = 1;
end
default:
halt = 1;
endcase
else if(cs == `EXECB)
begin
if(irout[15:12] == `PUSH|| irout[15:12] == `LD)
begin
ram2dbus = 1; dbus2qtop = 1; push = 1;
end
else
if(irout[15:12] == `ST)
begin
pop = 1;
end
end
end
endmodule
- state.v
`include "defs.v"
module state(clk, reset, run, cont, halt, cs
);
input clk, reset, run, cont, halt;
output [2:0] cs;
reg [2:0] cs;
always @(posedge clk or negedge reset)
if(!reset) cs<= `IDLE;
else
case(cs)
`IDLE: if(run) cs <= `FETCHA;
`FETCHA: cs <= `FETCHB;
`FETCHB: cs <= `EXECA;
`EXECA: if(halt) cs <= `IDLE;
else if(cont) cs <= `EXECB;
else cs <= `FETCHA;
`EXECB: cs <= `FETCHA;
default: cs <= 3'bxxx;
endcase
endmodule
- stack.v
module stack(clk, reset, load, push, pop, d, qtop, qnext...
parameter N=8;
input clk, reset, load, push, pop;
input [15:0] d;
output [15:0] qtop, qnext;
reg [15:0] q [N-1:0];
assign qtop = q[0];
assign qnext = q[1];
always @(posedge clk or negedge reset)
if(!reset) q[0] <= 0;
else if(load) q[0] <= d;
else if(pop) q[0] <= q[1];
//integer i;
generate
genvar i;
for(i=1;i<N-1; i=i+1)
begin : for_i
always @(posedge clk or negedge reset)
if(!reset) q[i] <=0;
else if(push) q[i] <=q[i-1];
else if(pop) q[i] <=q[i+1];
end
endgenerate
always @(posedge clk or negedge reset)
if(!reset) q[N-1] <= 0;
else if(push) q[N-1] <= q[N-2];
endmodule
- alu.v
`include "defs.v"
module alu(a,b,f,s);
input [15:0] a,b;
input [4:0] f;
output [15:0] s;
reg [15:0] s;
wire [15:0] x,y;
assign x=a+16'h8000;
assign y=b+16'h8000;
always @(a or b or x or y or f)
case(f)
`ADD : s = b + a;
`SUB : s = b - a;
`MUL : s = b * a;
`SHL : s = b << a;
`SHR : s = b >> a;
`BAND : s = b & a;
`BOR : s = b | a;
`BXOR : s = b ^ a;
`AND : s = b && a;
`OR : s = b || a;
`EQ : s = b == a;
`NE : s = b != a;
`GE : s = x >= y;
`LE : s = x <= y;
`GT : s = x > y;
`LT : s = x < y;
`NEG : s= -a;
`BNOT : s= ~a;
`NOT : s = !a;
default : s = 16'hxxxx;
endcase
endmodule
- ram.v
module ram(clk, load, addr, d, q
);
parameter DWIDTH=16, AWIDTH=12, WORDS=4096;
input clk, load;
input [AWIDTH-1:0] addr;
input [DWIDTH-1:0] d;
output [DWIDTH-1:0] q;
reg [DWIDTH-1:0] q;
reg [DWIDTH-1:0] mem [WORDS-1:0];
always @(posedge clk)
begin
if(load) mem[addr] <= d;
q <= mem[addr];
end
integer i;
initial begin
for(i=0; i<WORDS; i=i+1)
mem[i]=12'h000;
mem[8'h00] = 16'h1000; // PUSHI 0
mem[8'h01] = 16'h3021; // POP i ... i=0;
mem[8'h02] = 16'h2021; // L1 PUSH i
mem[8'h03] = 16'h1023; // PUSHI C
mem[8'h04] = 16'hF000; // ADD
mem[8'h05] = 16'h2021; // PUSH i
mem[8'h06] = 16'h8000; // ST ... C[i]=i;
mem[8'h07] = 16'h2021; // PUSH i
mem[8'h08] = 16'h1001; // PUSHI 1
mem[8'h09] = 16'hF000; // ADD
mem[8'h0A] = 16'h3021; // POP i .... i++;
mem[8'h0B] = 16'h2021; // PUSH i
mem[8'h0C] = 16'h201F; // PUSH n
mem[8'h0D] = 16'hF001; // SUB
mem[8'h0E] = 16'h6002; // JNZ L1: if(i<n) goto L1;
mem[8'h0F] = 16'h1000; // PUSHI 0
mem[8'h10] = 16'h3022; // POP j .... j=0;
mem[8'h11] = 16'h2022; // L2: PUSH j
mem[8'h12] = 16'h1023; // PUSHI C
mem[8'h13] = 16'hF000; // ADD
mem[8'h14] = 16'h7000; // LD
mem[8'h15] = 16'hE000; // OUT print(C[j]);
mem[8'h16] = 16'h2022; // PUSH j
mem[8'h17] = 16'h1001; // PUSHI 1
mem[8'h18] = 16'hF000; // ADD
mem[8'h19] = 16'h3022; // POP j j++
mem[8'h1A] = 16'h2022; // PUSH j
mem[8'h1B] = 16'h2020; // PUSH m
mem[8'h1C] = 16'hF001; // SUB
mem[8'h1D] = 16'h6011; // JNZ L2: if(j<m) goto L2
mem[8'h1E] = 16'h0000; // L3: HALT
mem[8'h1F] = 16'h0004; // n: 4
mem[8'h20] = 16'h0010; // m: 16
mem[8'h21] = 16'h0000; // i:
mem[8'h22] = 16'h0000; // j: 0
mem[8'h23] = 16'h0000; // C:
mem[8'h24] = 16'h0000; //
mem[8'h25] = 16'h0000; //
mem[8'h26] = 16'h0000; //
mem[8'h27] = 16'h0001; // D: 1
mem[8'h28] = 16'h0000; // 0
mem[8'h29] = 16'h0002; // 2
mem[8'h2A] = 16'h0000; // 0
mem[8'h2B] = 16'h0004; // 4
mem[8'h2C] = 16'h0000; // 0
mem[8'h2D] = 16'h0005; // 5
mem[8'h2E] = 16'h0000; // 0
mem[8'h2F] = 16'h000A; // A
mem[8'h30] = 16'h0000; // 0
mem[8'h31] = 16'h0008; // 8
mem[8'h32] = 16'h0000; // 0
end
endmodule
- counter.v
module counter(clk, reset, load, inc, d, q );
parameter N=16;
input clk, reset, load, inc;
input [N-1:0] d;
output [N-1:0] q;
reg [N-1:0] q;
always @(posedge clk or negedge reset)
if(!reset) q <=0;
else if(load) q<=d;
else if(inc) q<=q+1;
endmodule
- chattering.v
module chattering(clk, reset, in, out
);
parameter N=1;
input clk, reset;
input [N-1:0]in;
output [N-1:0]out;
reg [N-1:0]out;
reg [21:0] count;
always @(posedge clk or negedge reset)
if(!reset) count <=0;
else count <= count +1;
always @(posedge clk)
if(count==0) out <= in;
endmodule
- sSegArray.v
module sSegArray(
clk,reset,load,d,
anode, cathode
);
parameter N=32;
input clk,reset,load;
input [N-1:0] d;
output [7:0] anode;
output [7:0] cathode;
reg [7:0] anode;
reg [7:0] cathode;
reg [31:0] q;
wire [2:0] selectedSeg;
wire [7:0] wOneSeg;
reg segClk;
counter #(8) waitOneSeg(.clk(clk), .reset(reset), .load(...
//assign segClk= (wOneSeg==0)? ~segClk: segClk;
always @(posedge clk, negedge reset) begin
if(!reset) segClk<=0;
else
if (wOneSeg==0) segClk<=~segClk;
end
counter #(3) selector(.clk(segClk),.reset(reset),.load(0...
//counter #(3) selector(.clk(clk), .reset(reset), .load(...
always @(posedge clk, negedge reset)
begin
if(!reset) anode=8'hFE; // note! anode is connected...
else // in order to active one 7s...
case (selectedSeg)
3'b000: anode=8'hFE;
3'b001: anode=8'hFD;
3'b010: anode=8'hFB;
3'b011: anode=8'hF7;
3'b100: anode=8'hEF;
3'b101: anode=8'hDF;
3'b110: anode=8'hBF;
3'b111: anode=8'h7F;
endcase
end
reg [3:0] selectedVal;
always @(posedge clk, negedge reset)
begin
if(!reset) cathode=8'h03; // note! ...
else // and i...
case (selectedVal) // ...
4'b0000: cathode=8'h03; //8'hfc; 0 -...
4'b0001: cathode=8'h9f; //8'h60; 1 /...
4'b0010: cathode=8'h25; //8'hda; 2 /...
4'b0011: cathode=8'h0d; //8'hf2; 3 / ...
4'b0100: cathode=8'h99; //8'h66; 4 --...
4'b0101: cathode=8'h49; //8'hb6; 5 / cg...
4'b0110: cathode=8'h41; //8'hbe; 6 /ce...
4'b0111: cathode=8'h1f; //8'he0; 7 / ...
4'b1000: cathode=8'h01; //8'hfe; 8 --...
4'b1001: cathode=8'h09; //8'hf6; 9 ...
4'b1010: cathode=8'h11; //8'hee; A
4'b1011: cathode=8'hc1; //8'h3e; B
4'b1100: cathode=8'h63; //8'h9c; C
4'b1101: cathode=8'h85; //8'h7c; D
4'b1110: cathode=8'h61; //8'h9e; E
4'b1111: cathode=8'h71; //8'h8e; F
endcase
end
always @(posedge clk, negedge reset)
begin
if(!reset) selectedVal=q[3:0];
else
case (selectedSeg)
3'b000: selectedVal=q[3:0];
3'b001: selectedVal=q[7:4];
3'b010: selectedVal=q[11:8];
3'b011: selectedVal=q[15:12];
3'b100: selectedVal=q[19:16];
3'b101: selectedVal=q[23:20];
3'b110: selectedVal=q[27:24];
3'b111: selectedVal=q[31:28];
endcase
end
always @(posedge clk, negedge reset)
begin
if(!reset) q=0;
else
if(load) q=d;
end
endmodule
- top.xdc (vivadoの場合)
## Clock signal
##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name...
set_property PACKAGE_PIN E3 [get_ports bclck]
set_property IOSTANDARD LVCMOS33 [get_ports bclck]
# create_clock -add -name sys_clk_pin -period 10.00 -wa...
## Switches
##Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name ...
set_property PACKAGE_PIN U9 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
##Bank = 34, Pin name = IO_25_34, Sch name = SW1
set_property PACKAGE_PIN U8 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
##Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2
set_property PACKAGE_PIN R7 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
##Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3
set_property PACKAGE_PIN R6 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
##Bank = 34, Pin name = IO_L19N_T3_VREF_34, Sch name...
set_property PACKAGE_PIN R5 [get_ports {sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
##Bank = 34, Pin name = IO_L20P_T3_34, Sch name = SW5
set_property PACKAGE_PIN V7 [get_ports {sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
##Bank = 34, Pin name = IO_L20N_T3_34, Sch name = SW6
set_property PACKAGE_PIN V6 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
##Bank = 34, Pin name = IO_L10P_T1_34, Sch name = SW7
set_property PACKAGE_PIN V5 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
##Bank = 34, Pin name = IO_L8P_T1-34, Sch name = SW8
set_property PACKAGE_PIN U4 [get_ports {sw[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
##Bank = 34, Pin name = IO_L9N_T1_DQS_34, Sch name =...
set_property PACKAGE_PIN V2 [get_ports {sw[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
##Bank = 34, Pin name = IO_L9P_T1_DQS_34, Sch name =...
set_property PACKAGE_PIN U2 [get_ports {sw[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
##Bank = 34, Pin name = IO_L11N_T1_MRCC_34, Sch name...
set_property PACKAGE_PIN T3 [get_ports {sw[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
##Bank = 34, Pin name = IO_L17N_T2_34, Sch name = S...
set_property PACKAGE_PIN T1 [get_ports {sw[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
##Bank = 34, Pin name = IO_L11P_T1_SRCC_34, Sch name...
set_property PACKAGE_PIN R3 [get_ports {sw[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
##Bank = 34, Pin name = IO_L14N_T2_SRCC_34, Sch name...
set_property PACKAGE_PIN P3 [get_ports {sw[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
##Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name...
set_property PACKAGE_PIN P4 [get_ports {sw[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
## LEDs
##Bank = 34, Pin name = IO_L24N_T3_34, Sch name = L...
set_property PACKAGE_PIN T8 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
##Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name ...
set_property PACKAGE_PIN V9 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
##Bank = 34, Pin name = IO_L24P_T3_34, Sch name = L...
set_property PACKAGE_PIN R8 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
##Bank = 34, Pin name = IO_L23N_T3_34, Sch name = L...
set_property PACKAGE_PIN T6 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
##Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name...
set_property PACKAGE_PIN T5 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
##Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name...
set_property PACKAGE_PIN T4 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
##Bank = 34, Pin name = IO_L22P_T3_34, Sch name = L...
set_property PACKAGE_PIN U7 [get_ports {led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
##Bank = 34, Pin name = IO_L22N_T3_34, Sch name = L...
set_property PACKAGE_PIN U6 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
##Bank = 34, Pin name = IO_L10N_T1_34, Sch name = L...
set_property PACKAGE_PIN V4 [get_ports {led[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
##Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9
set_property PACKAGE_PIN U3 [get_ports {led[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
##Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LE...
set_property PACKAGE_PIN V1 [get_ports {led[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
##Bank = 34, Pin name = IO_L17P_T2_34, Sch name = L...
set_property PACKAGE_PIN R1 [get_ports {led[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
##Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name...
set_property PACKAGE_PIN P5 [get_ports {led[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
##Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LE...
set_property PACKAGE_PIN U1 [get_ports {led[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
##Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name ...
set_property PACKAGE_PIN R2 [get_ports {led[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
##Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name ...
set_property PACKAGE_PIN P2 [get_ports {led[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LE...
#set_property PACKAGE_PIN K5 [get_ports {cled1[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {cled1[2]}]
##Bank = 15, Pin name = IO_L5P_T0_AD9P_15, Sch name ...
#set_property PACKAGE_PIN F13 [get_ports {cled1[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {cled1[1]}]
##Bank = 35, Pin name = IO_L19N_T3_VREF_35, Sch name...
#set_property PACKAGE_PIN F6 [get_ports {cled1[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {cled1[0]}]
##Bank = 34, Pin name = IO_0_34, Sch name = LED17_R
#set_property PACKAGE_PIN K6 [get_ports {cled2[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {cled2[2]}]
##Bank = 35, Pin name = IO_24P_T3_35, Sch name = L...
#set_property PACKAGE_PIN H6 [get_ports {cled2[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {cled2[1]}]
##Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14, S...
#set_property PACKAGE_PIN L16 [get_ports {cled2[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {cled2[0]}]
##7 segment display
##Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA
set_property PACKAGE_PIN L3 [get_ports {sSegCathode[7]}]...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathod...
##Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name =...
set_property PACKAGE_PIN N1 [get_ports {sSegCathode[6]}]...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathod...
##Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name ...
set_property PACKAGE_PIN L5 [get_ports {sSegCathode[5]}]...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathod...
##Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD
set_property PACKAGE_PIN L4 [get_ports {sSegCathode[4]}]...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathod...
##Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE
set_property PACKAGE_PIN K3 [get_ports {sSegCathode[3]}]...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathod...
##Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF
set_property PACKAGE_PIN M2 [get_ports {sSegCathode[2]}]...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathod...
##Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG
set_property PACKAGE_PIN L6 [get_ports {sSegCathode[1]}]...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathod...
##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP
set_property PACKAGE_PIN M4 [get_ports sSegCathode[0]] ...
set_property IOSTANDARD LVCMOS33 [get_ports sSegCathode...
##Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0
set_property PACKAGE_PIN N6 [get_ports {sSegAnode[0]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1
set_property PACKAGE_PIN M6 [get_ports {sSegAnode[1]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2
set_property PACKAGE_PIN M3 [get_ports {sSegAnode[2]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name ...
set_property PACKAGE_PIN N5 [get_ports {sSegAnode[3]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name =...
set_property PACKAGE_PIN N2 [get_ports {sSegAnode[4]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5
set_property PACKAGE_PIN N4 [get_ports {sSegAnode[5]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6
set_property PACKAGE_PIN L1 [get_ports {sSegAnode[6]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7
set_property PACKAGE_PIN M1 [get_ports {sSegAnode[7]}] ...
set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[...
##Buttons
##Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15, Sch na...
#set_property PACKAGE_PIN C12 [get_ports btnCpuReset]
#set_property IOSTANDARD LVCMOS33 [get_ports btnCpuReset]
##Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name...
set_property PACKAGE_PIN E16 [get_ports bc]
set_property IOSTANDARD LVCMOS33 [get_ports bc]
##Bank = 15, Pin name = IO_L14P_T2_SRCC_15, Sch name...
set_property PACKAGE_PIN F15 [get_ports bu]
set_property IOSTANDARD LVCMOS33 [get_ports bu]
##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14...
set_property PACKAGE_PIN T16 [get_ports bl]
set_property IOSTANDARD LVCMOS33 [get_ports bl]
##Bank = 14, Pin name = IO_25_14, Sch name = BTNR
set_property PACKAGE_PIN R10 [get_ports br]
set_property IOSTANDARD LVCMOS33 [get_ports br]
##Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name ...
set_property PACKAGE_PIN V10 [get_ports bd]
set_property IOSTANDARD LVCMOS33 [get_ports bd]
##Temperature Sensor
##Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name...
#set_property PACKAGE_PIN F16 [get_ports scl]
#set_property IOSTANDARD LVCMOS33 [get_ports scl]
##Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name...
#set_property PACKAGE_PIN G16 [get_ports sda]
#set_property IOSTANDARD LVCMOS33 [get_ports sda]
##Bank = 15, Pin name = IO_L1P_T0_AD0P_15, Sch name ...
#set_property PACKAGE_PIN D14 [get_ports tmpInt]
#set_property IOSTANDARD LVCMOS33 [get_ports tmpInt]
##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name ...
#set_property PACKAGE_PIN C14 [get_ports tmpCT]
#set_property IOSTANDARD LVCMOS33 [get_ports tmpCT]
- top.ucf (ISEの場合)
## This file is a general .ucf for the Nexys4 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used signals according to the project
## Clock signal
NET "bclck" LOC = "E3" | IOSTANDARD = "LVCMOS33"; ...
#NET "clk" TNM_NET = sys_clk_pin;
#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100 MHz HI...
## Switches
NET "sw<0>" LOC = "U9" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<1>" LOC = "U8" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<2>" LOC = "R7" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<3>" LOC = "R6" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<4>" LOC = "R5" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<5>" LOC = "V7" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<6>" LOC = "V6" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<7>" LOC = "V5" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<8>" LOC = "U4" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<9>" LOC = "V2" | IOSTANDARD = "LVCMOS33"; #Ba...
NET "sw<10>" LOC = "U2" | IOSTANDARD = "LVCMOS33"; #B...
NET "sw<11>" LOC = "T3" | IOSTANDARD = "LVCMOS33"; #B...
NET "sw<12>" LOC = "T1" | IOSTANDARD = "LVCMOS33"; #B...
NET "sw<13>" LOC = "R3" | IOSTANDARD = "LVCMOS33"; #B...
NET "sw<14>" LOC = "P3" | IOSTANDARD = "LVCMOS33"; #B...
NET "sw<15>" LOC = "P4" | IOSTANDARD = "LVCMOS33"; #B...
## LEDs
NET "led<0>" LOC = "T8" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<1>" LOC = "V9" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<2>" LOC = "R8" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<3>" LOC = "T6" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<4>" LOC = "T5" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<5>" LOC = "T4" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<6>" LOC = "U7" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<7>" LOC = "U6" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<8>" LOC = "V4" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<9>" LOC = "U3" | IOSTANDARD = "LVCMOS33"; #B...
NET "led<10>" LOC = "V1" | IOSTANDARD = "LVCMOS33"; #...
NET "led<11>" LOC = "R1" | IOSTANDARD = "LVCMOS33"; #...
NET "led<12>" LOC = "P5" | IOSTANDARD = "LVCMOS33"; #...
NET "led<13>" LOC = "U1" | IOSTANDARD = "LVCMOS33"; #...
NET "led<14>" LOC = "R2" | IOSTANDARD = "LVCMOS33"; #...
NET "led<15>" LOC = "P2" | IOSTANDARD = "LVCMOS33"; #...
#NET "RGB1_Red" LOC = "K5" | IOSTANDARD = "LVCMOS33"; ...
#NET "RGB1_Green" LOC = "F13" | IOSTANDARD = "LVCMOS33"...
#NET "RGB1_Blue" LOC = "F6" | IOSTANDARD = "LVCMOS33"; ...
#NET "RGB2_Red" LOC = "K6" | IOSTANDARD = "LVCMOS33"; ...
#NET "RGB2_Green" LOC = "H6" | IOSTANDARD = "LVCMOS33";...
#NET "RGB2_Blue" LOC = "L16" | IOSTANDARD = "LVCMOS33";...
## 7 segment display
NET "sSegCathode<7>" LOC = "L3" | IOSTANDARD = "LVCMOS...
NET "sSegCathode<6>" LOC = "N1" | IOSTANDARD = "LVCMOS...
NET "sSegCathode<5>" LOC = "L5" | IOSTANDARD = "LVCMOS...
NET "sSegCathode<4>" LOC = "L4" | IOSTANDARD = "LVCMOS...
NET "sSegCathode<3>" LOC = "K3" | IOSTANDARD = "LVCMOS...
NET "sSegCathode<2>" LOC = "M2" | IOSTANDARD = "LVCMOS...
NET "sSegCathode<1>" LOC = "L6" | IOSTANDARD = "LVCMOS...
NET "sSegCathode<0>" LOC = "M4" | IOSTANDARD = "LVCMO...
NET "sSegAnode<0>" LOC = "N6" | IOSTANDARD = "LVCMOS33...
NET "sSegAnode<1>" LOC = "M6" | IOSTANDARD = "LVCMOS33...
NET "sSegAnode<2>" LOC = "M3" | IOSTANDARD = "LVCMOS33...
NET "sSegAnode<3>" LOC = "N5" | IOSTANDARD = "LVCMOS33...
NET "sSegAnode<4>" LOC = "N2" | IOSTANDARD = "LVCMOS33...
NET "sSegAnode<5>" LOC = "N4" | IOSTANDARD = "LVCMOS33...
NET "sSegAnode<6>" LOC = "L1" | IOSTANDARD = "LVCMOS33...
NET "sSegAnode<7>" LOC = "M1" | IOSTANDARD = "LVCMOS33...
## Buttons
#NET "btnCpuReset" LOC = "C12" | IOSTANDARD = "LVCMOS33...
NET "bc" LOC = "E16" | IOSTANDARD = "LVCMOS33"; #Ban...
NET "bu" LOC = "F15" | IOSTANDARD = "LVCMOS33"; #Ban...
NET "bl" LOC = "T16" | IOSTANDARD = "LVCMOS33"; #Ban...
NET "br" LOC = "R10" | IOSTANDARD = "LVCMOS33"; #Ban...
NET "bd" LOC = "V10" | IOSTANDARD = "LVCMOS33"; #Ban...
* 動かし方 [#k3a2a93b]
** Nexys4へのbitファイル書き込み [#id3441e9]
- 上のソースを使ってVivadoかISEで bit ファイルを生成し, N...
-- Nexys4のBTNC(bc)を minicpu の clock ボタン, BTNU(bu)を...
-- Nexys4の8桁の7セグメント LEDの、いちばん左の桁はminiCP...
-- 7セグメントLEDの左から２桁目、３桁目、４桁目は、 minic...
-- Nexyx4の16個のLEDは, minicpuの出力バッファの出力(out)...
** CPUの実行 [#xb98452f]
- bd(reset)をクリックしてcpuをresetします。
- bu(run) を押して、そのままbc(bclck)を押して離して最初の...
- bcを何度も押して離して、cpuにclockを供給し、実行を進め...
- 一番左の桁が1(fetch a state)のときの、左から２桁目から...
- 上のプログラムは配列Cに、0,1,2,3を代入し、その内容を出...
----
#counter
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