top.v
module top(sSegAnode, sSegCathode, sw, ledOut, colorLed_1, colorLed_2,
bu, bd, bl, br, bc, scl, sda,
bclck
);
output [7:0] sSegAnode;
output [7:0] sSegCathode;
output [15:0] ledOut; // led[8] ... if sda is sending, corresponding to the last sended sda,
else corresponding to the last received sda
// it is shifted to left when a positive edge of scl is detected.
// led[0] corresponding to sw[0]
// led[1] corresponding to sw[1]
// led[2] corresponsing to center button, bc.
output [2:0] colorLed_1;
output [2:0] colorLed_2; // color LED
input [15:0] sw; // sw[15:8] ... for setting sda send data, sw[7:0] ... for controlling
// sw[0] ... if 1 scl is not ready, else scl is ready;
// sw[1] ... if 1 sda is receiving(1), else sda is sending(0).
// sw[2] ... sending sda.
input bu, bd, bl, br, bc, bclck; // bd corresponding to !reset.
// bc corresponding to scl. scl=sw[0]|bc
// if posedge bl is detected, sw is shown in hex in the 7seg led array.
inout scl, sda;
reg sclx, sdax;
assign scl=(~sclx)?1'b0:1'bz;
assign sda=(~sdax)?1'b0:1'bz;
wire BNx, BWx, BEx, BCx;
// reset: BSx
// BWx, BEx ... change operationMode
//
wire [15:0] swx;
wire reset;
// reg sclRw, sdaRw; // write=1, read=0;
wire cpuClk;
wire cpuRun;
reg [7:0] data;
reg [2:0] operationMode;
// operationMode: 0 ... manual operation of peripherals
// 1 ... CPU independent
// 2 ... CPU, I2C connected
reg [15:0] ledWire,cpuIn;
wire [2:0] cpuCs;
wire [11:0] pcout,abus;
wire [15:0] irout,qtop,dbus,out;
reg [31:0] sSegArray;
reg [15:0] led;
wire start;
wire haltIn;
wire halt;
reg [4:0] divide;
wire dclk;
assign ledOut=led;
reg [2:0] colorLed_1x;
wire [2:0] colorLed_2x;
//
assign colorLed_1=colorLed_1x;
assign colorLed_2=colorLed_2x;
assign reset=~bd;
always @(posedge sclx, negedge reset) begin
if(!reset) begin
data<=0;
end
else
data<={data[6:0],sda};
end
// for operation mode
always @(posedge BEx or negedge reset ) begin
if(!reset) begin
operationMode<=3'b000;
end
else
case (operationMode)
3'b000: operationMode<=3'b001;
3'b001: operationMode<=3'b010;
3'b010: operationMode<=3'b011;
3'b011: operationMode<=3'b100;
3'b100: operationMode<=3'b101;
3'b101: operationMode<=3'b110;
3'b110: operationMode<=3'b000;
default
operationMode<=3'b000;
endcase
end
/*
always @(posedge BWx or negedge reset ) begin
if(!reset) begin
operationMode<=0;
end
else
case (operationMode)
3'b000: operationMode<=3'b110;
3'b001: operationMode<=3'b000;
3'b010: operationMode<=3'b001;
3'b011: operationMode<=3'b010;
3'b100: operationMode<=3'b011;
3'b101: operationMode<=3'b100;
3'b110: operationMode<=3'b101;
default
operationMode<=3'b000;
endcase
end
*/
/* */
// assign setDivide=(operationMode==3'b011)?BCx:1'b0;
always @(posedge BCx ) begin
if(operationMode==3'b011) begin
divide<=swx[15:11];
end
end
assign colorLed_2x={dclk,scl,sda};
assign start=(operationMode==3'b100|operationMode==3'b101)?BCx:1'b0;
assign cpuClk=(operationMode==3'b100|operationMode==3'b101)? dclk:BCx;
assign cpuRun=(operationMode==3'b100|operationMode==3'b101)? ssRun:BNx;
assign haltIn=(operationMode==3'b100|operationMode==3'b101)? halt:1'b0;
// always @(operationMode or swx[0] or BCx or data or BNx or cpuCs or out or sda or scl or out[0] or out[1]) begin
// always @(posedge BEx or posedge BWx or negedge reset) begin
always @(operationMode) begin
case(operationMode)
3'b000: begin // direct i2c operation only
colorLed_1x=3'b000;
cpuIn=0;
sSegArray={{16{0}},data,swx[7:0]};
led[15:8]=data;
led[7:0]=swx[7:0];
sclx=BCx;
sdax=swx[0];
end
3'b001: begin // mini CPU, with manual clock only ... for start ... push BTN, keep, push BTC, release BTN, BTC
colorLed_1x=3'b001; // blue
cpuIn=swx;
sSegArray={{0},cpuCs,pcout,irout};
led={{0{16}},out};
sclx=1'b1;
sdax=1'b1;
end
3'b010: begin // mini CPU, with manual clock, with i2c IO
colorLed_1x=3'b010; //green
cpuIn={{8{0}},data};
sSegArray={{0},cpuCs,abus,dbus};
led[15:8]=data;
led[7:0]=out[7:0];
sclx=out[1];
sdax=out[0];
end
3'b011: begin // set clock divider for mini CPU with automatic clock
colorLed_1x=3'b011; // cyan .. aqua
cpuIn=0;
sSegArray={divide,{13{0}},data,swx[7:0]};
led[15:8]=divide;
led[7:0]=swx[7:0];
sclx=1;
sdax=1;
end
3'b100: begin // mini CPU, only, with automatic clock,
colorLed_1x=3'b100; // red
cpuIn=swx;
sSegArray={{0},cpuCs,pcout,irout};
led={{0{16}},out};
sclx=1'b1;
sdax=1'b1;
end
3'b101: begin // mini CPU, with automatic clock, with i2c IO
colorLed_1x=3'b101; // purple
cpuIn={{8{0}},data};
sSegArray={{0},cpuCs,abus,dbus};
led[15:8]=data;
led[7:0]=out[7:0];
sclx=out[1];
sdax=out[0];
end
default begin
colorLed_1x=3'b000;
cpuIn=swx;
sSegArray={{0{16}},data,swx[7:0]};
led[15:8]=data;
led[7:0]=swx[7:0];
sclx=BCx;
sdax=swx[0];
end
endcase
end
chattering #(20) chattering0(.clk(bclck), .reset(reset), .in({bu,bl,br,bc,sw}), .out({BNx, BWx, BEx, BCx,swx}));
/* for test bench
assign BNx=bu;
assign BWx=bl;
assign BEx=br;
assign BCx=bc;
assign swx=sw;
*/
sSegArray sSegArray0(.clk(bclck), .reset(reset), .load(1'b1), .d(sSegArray), .anode(sSegAnode), .cathode(sSegCathode));
minicpu minicpu0(.clk(cpuClk), .reset(reset), .run(cpuRun), .in(cpuIn), .cs(cpuCs), .pcout(pcout),
.irout(irout), .qtop(qtop), .abus(abus), .dbus(dbus), .out(out), .haltx(haltIn));
clockDivider clockDivider0(.clk(bclck),.reset(reset), .div(divide), .dclk(dclk));
cpuStartStopSequence cpuStartStopSequence0(.clk(dclk), .reset(reset), .start(start), .run(ssRun), .halt(halt));
endmodule![[PukiWiki]](image/pukiwiki.png "[PukiWiki]")
