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| operationMode | 機能 | Color LED 1 | cpuClk | cpuRun | cpuIn | sSegArray | led | sclx, sdax | Color LED 2 | start |
| 0 | I2Cバスの手動操作 | {0,0,0} | BCx | 0 | 0 | {16{0}, data,swx[7:0]} | {data,swx[7:0]} | BCx,swx[0] | {0,sda,scl} | 0 |
| 1 | miniCPUの独立実行(手動クロック供給) | {0,0,1} | BCx | BNx | swx | {sSegBufH,sSegBufL} | out | 1,1 | {0,sda,scl} | 0 |
| 2 | miniCPUでI2Cバスを操作(手動クロック供給) | {0,1,0} | BCx | BNx | {8{0},data} | {sSegBufH,sSegBufL} | {data,out[7:0]} | out[1],out[0] | {0,sda,scl} | 0 |
| 3 | miniCPU自動クロック供給のときのクロック分周値設定 | {0,1,1} | BCx | 0 | {8{0},data} | {{0},cpuCs,abus,dbus} | {data,out[7:0]} | out[1],out[0] | {0,sda,scl} | 0 |
| 4 | miniCPUの独立実行(自動クロック供給) | {1,0,0} | dclk | ssRun(自動スタート) | swx | {sSegBufH,sSegBufL} | out | 1,1 | {0,sda,scl} | BCx |
| 5 | miniCPUでI2Cバスを操作(自動クロック供給) | {1,0,1} | dclk | ssRun(自動スタート) | {8{0},data} | sSegBufH,sSegBufL} | {data,out[7:0]} | out[1],out[0] | {0,sda,scl} | BCx |
module top(sSegAnode, sSegCathode, sw, ledOut, colorLed_1, colorLed_2,
bu, bd, bl, br, bc, scl, sda, jc,
bclck
);
output [7:0] sSegAnode;
output [7:0] sSegCathode;
output [15:0] ledOut; // led[8] ... if sda is sending, corresponding to the last sended sda, else corresponding to the last received sda
// it is shifted to left when a positive edge of scl is detected.
// led[0] corresponding to sw[0]
// led[1] corresponding to sw[1]
// led[2] corresponsing to center button, bc.
output [2:0] colorLed_1;
output [2:0] colorLed_2; // color LED
output [3:0] jc;
input [15:0] sw; // sw[15:8] ... for setting sda send data, sw[7:0] ... for controlling
// sw[0] ... if 1 scl is not ready, else scl is ready;
// sw[1] ... if 1 sda is receiving(1), else sda is sending(0).
// sw[2] ... sending sda.
input bu, bd, bl, br, bc, bclck; // bd corresponding to !reset.
// bc corresponding to scl. scl=sw[0]|bc
// if posedge bl is detected, sw is shown in hex in the 7seg led array.
inout scl, sda;
reg sclx, sdax;
reg [3:0] jcx;
assign scl=(~sclx)?1'b0:1'bz;
assign sda=(~sdax)?1'b0:1'bz;
assign jc=jcx;
wire BNx, BWx, BEx, BCx;
// reset: BSx
// BWx, BEx ... change operationMode
//
wire [15:0] swx;
wire reset;
// reg sclRw, sdaRw; // write=1, read=0;
wire cpuClk;
wire cpuRun;
reg [7:0] data;
reg [2:0] operationMode;
// operationMode: 0 ... manual operation of peripherals
// 1 ... CPU independent
// 2 ... CPU, I2C connected
reg [15:0] ledWire,cpuIn;
wire [2:0] cpuCs;
wire [11:0] pcout,abus;
wire [15:0] irout,qtop,dbus,out;
reg [31:0] sSegArray;
reg [15:0] led;
wire start;
wire haltIn;
wire halt;
wire [15:0] sSegBufL;
wire [15:0] sSegBufH;
reg [4:0] divide;
wire dclk;
initial begin
divide={01101};
end
assign ledOut=led;
reg [2:0] colorLed_1x;
wire [2:0] colorLed_2x;
//
assign colorLed_1=colorLed_1x;
assign colorLed_2=colorLed_2x;
assign reset=~bd;
always @(posedge sclx, negedge reset) begin
if(!reset) begin
data<=0;
end
else
data<={data[6:0],sda};
end
// for operation mode
always @(posedge BEx or negedge reset ) begin
if(!reset) begin
operationMode<=3'b000;
end
else
case (operationMode)
3'b000: operationMode<=3'b001;
3'b001: operationMode<=3'b010;
3'b010: operationMode<=3'b011;
3'b011: operationMode<=3'b100;
3'b100: operationMode<=3'b101;
3'b101: operationMode<=3'b110;
3'b110: operationMode<=3'b000;
default
operationMode<=3'b000;
endcase
end
/*
always @(posedge BWx or negedge reset ) begin
if(!reset) begin
operationMode<=0;
end
else
case (operationMode)
3'b000: operationMode<=3'b110;
3'b001: operationMode<=3'b000;
3'b010: operationMode<=3'b001;
3'b011: operationMode<=3'b010;
3'b100: operationMode<=3'b011;
3'b101: operationMode<=3'b100;
3'b110: operationMode<=3'b101;
default
operationMode<=3'b000;
endcase
end
*/
/* */
// assign setDivide=(operationMode==3'b011)?BCx:1'b0;
always @(posedge BCx ) begin
if(operationMode==3'b011) begin
divide<=swx[15:11];
end
end
assign colorLed_2x={dclk,scl,sda};
assign start=(operationMode==3'b100|operationMode==3'b101)?BCx:1'b0;
assign cpuClk=(operationMode==3'b100|operationMode==3'b101)? dclk:BCx;
assign cpuRun=(operationMode==3'b100|operationMode==3'b101)? ssRun:BNx;
assign haltIn=(operationMode==3'b100|operationMode==3'b101)? halt:1'b0;
assign sSegBufL=BWx?irout:out;
assign sSegBufH=BWx?{{0},cpuCs,abus}:pcout;
// always @(operationMode or swx[0] or BCx or data or BNx or cpuCs or out or sda or scl or out[0] or out[1]) begin
// always @(posedge BEx or posedge BWx or negedge reset) begin
always @(operationMode) begin
case(operationMode)
3'b000: begin // direct i2c operation only
colorLed_1x=3'b000;
cpuIn=0;
sSegArray={{16{0}},data,swx[7:0]};
led[15:8]=data;
led[7:0]=swx[7:0];
sclx=BCx;
sdax=swx[0];
jcx=swx[5:2];
end
3'b001: begin // mini CPU, with manual clock only ... for start ... push BTN, keep, push BTC, release BTN, BTC
colorLed_1x=3'b001; // blue
cpuIn=swx;
sSegArray={sSegBufH,sSegBufL};
led=out;
sclx=1'b1;
sdax=1'b1;
jcx={0,0,0,0};
end
3'b010: begin // mini CPU, with manual clock, with i2c IO
colorLed_1x=3'b010; //green
cpuIn={swx[15:8],data};
sSegArray={sSegBufH, sSegBufL};
led[15:8]=data;
led[7:0]=out[7:0];
sclx=out[1];
sdax=out[0];
jcx=out[5:2];
end
3'b011: begin // set clock divider for mini CPU with automatic clock
colorLed_1x=3'b011; // cyan .. aqua
cpuIn=0;
sSegArray={divide,{13{0}},data,swx[7:0]};
led[15:8]=divide;
led[7:0]=swx[7:0];
sclx=1;
sdax=1;
jcx={0,0,0,0};
end
3'b100: begin // mini CPU, only, with automatic clock,
colorLed_1x=3'b100; // red
cpuIn=swx;
sSegArray={sSegBufH, sSegBufL};
led=out;
sclx=1'b1;
sdax=1'b1;
jcx={0,0,0,0};
end
3'b101: begin // mini CPU, with automatic clock, with i2c IO
colorLed_1x=3'b101; // purple
cpuIn={swx[15:8],data};
sSegArray={sSegBufH, sSegBufL};
led[15:8]=data;
led[7:0]=out[7:0];
sclx=out[1];
sdax=out[0];
jcx=out[5:2];
end
default begin
colorLed_1x=3'b000;
cpuIn=swx;
sSegArray={{0{16}},data,swx[7:0]};
led[15:8]=data;
led[7:0]=swx[7:0];
sclx=BCx;
sdax=swx[0];
jcx=swx[5:2];
end
endcase
end
chattering #(20) chattering0(.clk(bclck), .reset(reset), .in({bu,bl,br,bc,sw}), .out({BNx, BWx, BEx, BCx,swx}));
/* for test bench
assign BNx=bu;
assign BWx=bl;
assign BEx=br;
assign BCx=bc;
assign swx=sw;
*/
sSegArray sSegArray0(.clk(bclck), .reset(reset), .load(1'b1), .d(sSegArray), .anode(sSegAnode), .cathode(sSegCathode));
minicpu minicpu0(.clk(cpuClk), .reset(reset), .run(cpuRun), .in(cpuIn), .cs(cpuCs), .pcout(pcout),
.irout(irout), .qtop(qtop), .abus(abus), .dbus(dbus), .out(out), .haltx(haltIn));
clockDivider clockDivider0(.clk(bclck),.reset(reset), .div(divide), .dclk(dclk));
cpuStartStopSequence cpuStartStopSequence0(.clk(dclk), .reset(reset), .start(start), .run(ssRun), .halt(halt));
endmodulemodule chattering(clk, reset, in, out ); parameter N=1; input clk, reset; input [N-1:0]in; output [N-1:0]out; reg [N-1:0]out; reg [21:0] count; always @(posedge clk or negedge reset) if(!reset) count <=0; else count <= count +1; always @(posedge clk) if(count==0) out <= in; endmodule
module sSegArray(
clk,reset,load,d,
anode, cathode
);
parameter N=32;
input clk,reset,load;
input [N-1:0] d;
output [7:0] anode;
output [7:0] cathode;
reg [7:0] anode;
reg [7:0] cathode;
reg [31:0] q;
wire [2:0] selectedSeg;
wire [7:0] wOneSeg;
reg segClk;
counter #(8) waitOneSeg(.clk(clk), .reset(reset), .load(1'b0), .inc(1'b1), .d(16'h0000), .q(wOneSeg));
//assign segClk= (wOneSeg==0)? ~segClk: segClk;
always @(posedge clk, negedge reset) begin
if(!reset) segClk<=0;
else
if (wOneSeg==0) segClk<=~segClk;
end
counter #(3) selector(.clk(segClk),.reset(reset),.load(1'b0), .inc(1'b1), .d(4'h0), .q(selectedSeg));
//counter #(3) selector(.clk(clk), .reset(reset), .load(0), .inc(1), .d(4'h0), .q(selectedSeg));
always @(posedge clk, negedge reset)
begin
if(!reset) anode=8'hFE; // note! anode is connected by pnp transistor.
else // in order to active one 7seg, low should be setted to the 7seg.
case (selectedSeg)
3'b000: anode=8'hFE;
3'b001: anode=8'hFD;
3'b010: anode=8'hFB;
3'b011: anode=8'hF7;
3'b100: anode=8'hEF;
3'b101: anode=8'hDF;
3'b110: anode=8'hBF;
3'b111: anode=8'h7F;
endcase
end
reg [3:0] selectedVal;
always @(posedge clk, negedge reset)
begin
if(!reset) cathode=8'h03; // note! when one segment of the cathode is low,
else // and its anode is low, the segment glow.
case (selectedVal) // ca
4'b0000: cathode=8'h03; //8'hfc; 0 ------
4'b0001: cathode=8'h9f; //8'h60; 1 / /
4'b0010: cathode=8'h25; //8'hda; 2 /cf / cb
4'b0011: cathode=8'h0d; //8'hf2; 3 / /
4'b0100: cathode=8'h99; //8'h66; 4 -----
4'b0101: cathode=8'h49; //8'hb6; 5 / cg /
4'b0110: cathode=8'h41; //8'hbe; 6 /ce / cc
4'b0111: cathode=8'h1f; //8'he0; 7 / /
4'b1000: cathode=8'h01; //8'hfe; 8 ------ . ch
4'b1001: cathode=8'h09; //8'hf6; 9 cd
4'b1010: cathode=8'h11; //8'hee; A
4'b1011: cathode=8'hc1; //8'h3e; B
4'b1100: cathode=8'h63; //8'h9c; C
4'b1101: cathode=8'h85; //8'h7c; D
4'b1110: cathode=8'h61; //8'h9e; E
4'b1111: cathode=8'h71; //8'h8e; F
endcase
end
always @(posedge clk, negedge reset)
begin
if(!reset) selectedVal=q[3:0];
else
case (selectedSeg)
3'b000: selectedVal=q[3:0];
3'b001: selectedVal=q[7:4];
3'b010: selectedVal=q[11:8];
3'b011: selectedVal=q[15:12];
3'b100: selectedVal=q[19:16];
3'b101: selectedVal=q[23:20];
3'b110: selectedVal=q[27:24];
3'b111: selectedVal=q[31:28];
endcase
end
always @(posedge clk, negedge reset)
begin
if(!reset) q=0;
else
if(load) q=d;
end
endmodulemodule clockDivider(clk, reset, div, dclk);
input clk, reset;
input [4:0] div;
output dclk;
reg dclk;
reg [31:0] q;
always @(posedge clk or negedge reset) begin
if(!reset)
q <=0;
else q<=q+1;
end
always @(posedge clk) begin
dclk<=q[div];
end
endmodulemodule cpuStartStopSequence(clk, reset, start, run, halt
);
input clk, reset, start;
reg [3:0] cs;
output run;
reg run;
output halt;
reg halt;
always @(posedge clk or negedge reset)
if(!reset) begin
cs<= 4'b0000;
run<=1'b0;
halt<=1'b0;
end
else
case(cs)
4'b0000: if(start) begin
cs <= 4'b0001;
end
4'b0001: if(!start) begin
cs <= 4'b0010;
run <= 1;
end
4'b0010: cs <= 4'b0011;
4'b0011: begin
cs <= 4'b0100;
run <=0;
end
4'b0100: if(start ) begin
cs <= 4'b0101;
end
4'b0101: begin
cs <= 4'b0110;
halt <=1'b1;
end
4'b0110: cs <= 4'b0111;
4'b0111: cs <= 4'b1000;
4'b1000: cs <= 4'b1001;
4'b1001: begin
cs <= 4'b0000;
halt <=1'b0;
end
default: cs <= 3'bxxx;
endcase
endmodule
